The present disclosure relates generally to semiconductor manufacturing and, more particularly, to a method for fabricating a stacked semiconductor device.
Vias have been routinely used in semiconductor fabrication to provide electrical coupling between one or more layers of conductive material within a semiconductor device. More recently, through-silicon vias (TSV) have arisen as a method of overcoming limitations of conventional wire bonding for example, as performance and density requirements increase no longer allowing traditional wire bonding to be adequate. TSV allow for shorter interconnects by forming an interconnect in the z-axis. The interconnect is created through a substrate (e.g. wafer), by forming a via extending from a front surface to a back surface of the substrate. TSV are also useful in forming interconnects for stacked wafers, stacked chip, and/or combinations thereof for 3-D packaging technologies.
In fabricating stacked semiconductor devices, a liquid no-flow underfill (NFU) including a flux is typically used for stacking and coupling two devices. The NFU layer is subjected to a thermal process (e.g., curing/reflow cycle) in which the NFU layer is cured and encapsulates the structures in a region between the devices. Also, solder bumps of one of the devices are reflowed and form a solder joint with TSV structures of the other device such that the devices become electrically coupled. For each additional device that is to be stacked and coupled, an additional NFU layer is provided and the thermal process is repeated. Although this method has been satisfactory for its intended purpose, it has not been satisfactory in all respects. One of the disadvantages is that the lower NFU layers are subjected to many curing/reflow cycles during the fabrication of stacked semiconductor device. This may increase the thermal stress of the NFU layer, and may induce various defects such as voids in the NFU layer, bump cracks or fracture, and peeling of the NFU layer, and thus may lead to poor device performance and reliability.
Therefore, a need exists for a method for fabricating a stacked semiconductor device that reduces the thermal stress of the coating material between devices.